I'm trying to build a binary clock with some surplus digital logic chips I have laying around. The chip of choice it seems would be the 7490, of which I have 1 that works properly and 1 that seems to only work if I leave it in the default mode of counting from 0 to 9. I also have a number of chips stamped with MCC838, which turns out to be a decade counter like the 7490.

The main exception is the 838 has 4 inputs to explicitly set the bits with and a single reset line. I need to configure 3 counters to reset after reaching 5 (on 6 reset to 0). With the 7490, just tie the second bit to one reset and the third bit to the other reset and assuming the chip works, it counts 0, 1, 2, 3, 4, 5, 0, ....

Studying the spec sheet I could find on the MC838 leads me to believe that by using a NAND gate on bits 2 & 3 the result should nicely drive the CD (reset) line from High-to-Low and hence reset the counter back to 0. However, that is not what is happening. Hear is the observed output:

1 2 4 8 NAND

0 0 0 0 1

1 0 0 0 1

0 1 0 0 1

1 1 0 0 1

0 0 1 0 1

1 0 1 0 1 - at this point, the next clock should create 0110 (6) and the NAND goes low (0) which should reset the 838 counter and start over. However, the counter just skips 6 & 7 and carries on with 8 as follows...

0 0 0 1 1

1 0 0 1 1

0 0 0 0 1

Any ideas?